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TDF8599TH 데이터시트(PDF) 11 Page - NXP Semiconductors

부품명 TDF8599TH
상세설명  I2C-bus controlled dual channel 43 W/2 W single channel 85 W/1 W class-D power amplifier with load diagnostics
PDF  52 Pages
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제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo NXP - NXP Semiconductors

TDF8599TH 데이터시트(HTML) 11 Page - NXP Semiconductors

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TDF8599_1
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 13 November 2008
11 of 52
NXP Semiconductors
TDF8599
Class-D power amplifier with load diagnostics
directly. Values for CPLL_s, CPLL_p and RPLL depend on the desired loop bandwidth
(BWPLL) of the PLL. RPLL is given by: RPLL = 8.4 × BWPLL Ω. The corresponding values for
CPLL_s and CPLL_p are given by:
(3)
Remark: CPLL_P is only needed when π/4 phase shift is selected. See Section 8.4.2 for
more detailed information.
(4)
When pin OSCIO is connected to a clock-master with Spread spectrum mode enabled,
the PLL loop bandwidth BWPLL should be 100 × fSSM.
See Table 7 for all oscillator modes.
8.4 Operation mode selection
Pin MOD is used to select specific operation modes. The resistor (RMOD) connected
between pins MOD and AGND determines the operation mode. The mode of operation
depends on whether non-I2C-bus mode or I2C-bus mode is active. This is in turn
determined by the resistor value connected between pins ADS and AGND.
a. Off
b. On
Fig 9.
Phase lock operation
Table 7.
Oscillator modes
OSCSET pin
OSCIO pin
SSM pin
Oscillator modes
Rosc > 26 kΩ
output
Cssm
master, spread spectrum
Rosc > 26 kΩ
output
shorted to AGND
master, no spread spectrum
Rosc =0 Ω
input
CPLL + RPLL
slave, PLL enabled
Rosc =0 Ω
input
shorted to AGND
slave, PLL disabled
C
PLL_p
0.032
R
PLL
BW
PLL
×
------------------------------------ F
[]
=
C
PLL_s
0.8
R
PLL
BW
PLL
×
------------------------------------ F
[]
=
001aai776
100
µA
SSM
OSCSET
PLL
001aai777
100
µA
PLL
OSCSET
RPLL
CPLL_P(1)
CPLL_s
SSM



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