CS43L22 datasheet(56/68 Pages) CIRRUS

56 / 68 page

DS792F1

CS43L22

Confidential Draft

10/7/08

7.25

Limiter Attack Rate (Address 29h)

7.25.1

Limiter Attack Rate

Sets the rate at which the limiter applies digital attenuation from levels above the MAX[2:0] threshold

(“Limiter Maximum Threshold” on page 54).

Note:

The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and

the DIGSFT (“Digital Soft Ramp” on page 45) and DIGZC (“Digital Zero Cross” on page 46) setting unless

the respective disable bit (“Limiter Soft Ramp Disable” on page 54 or “Limiter Zero Cross Disable” on

page 55) is enabled.

7.26

Status (Address 2Eh) (Read Only)

For all bits in this register, a “1” means the associated error condition has occurred at least once since the

of the register. Reading the register resets all bits to 0.

7.26.1

Serial Port Clock Error (Read Only)

Indicates the status of the MCLK to LRCK ratio.

Note:

On initial power up and application of clocks, this bit will report ‘1’b as the serial port re-synchro-

nizes.

7.26.2

DSP Engine Overflow (Read Only)

Indicates the over-range status in the DSP data path.

543

Reserved

LIMARATE5

LIMARATE4

LIMARATE3

LIMARATE2

LIMARATE1

LIMARATE0

LIMARATE[5:0]

Attack Time

00 0000

Fastest Attack

···

11 1111

Slowest Attack

Application:

“Limiter” on page 23

543

Reserved

SPCLKERR

DSPAOVFL

DSPBOVFL

PCMAOVFL

PCMBOVFL

Reserved

SPCLKERR

Serial Port Clock Status:

MCLK/LRCK ratio is valid.

MCLK/LRCK ratio is not valid.

Application:

“Serial Port Clocking” on page 30

DSPxOVFL

DSP Overflow Status:

No digital clipping has occurred in the data path after the DSP.

Digital clipping has occurred in the data path after the DSP.

Application:

“DSP Engine” on page 22

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