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CS4384 데이터시트(PDF) 39 Page - Cirrus Logic

부품명 CS4384
상세설명  103 dB, 192 kHz 8-Channel D/A Converter
PDF  52 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4384 데이터시트(HTML) 39 Page - Cirrus Logic

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DS620F1
39
CS4384
6.5
Filter Control (Address 05h)
6.5.1
Interpolation Filter Select (FILT_SEL)
Function:
When set to 0 (default), the Interpolation Filter has a fast roll off.
When set to 1, the Interpolation Filter has a slow roll off.
The specifications for each filter can be found in the Analog characteristics table, and response plots can
be found in Figures 26 to 49.
6.6
Invert Control (Address 06h)
6.6.1
Invert Signal Polarity (INV_xx)
Function:
When set to 1, this bit inverts the signal polarity of channel xx.
When set to 0 (default), this function is disabled.
6.7
Group Control (Address 07h)
6.7.1
Mutec Pin Control (MUTEC)
Default = 0
0 - Two Mute control signals
1 - Single mute control signal on MUTEC1
Function:
Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to ‘0’,
a logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the mute
control signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to ‘1’, a logical AND of all
DAC pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For more in-
formation on the use of the mute control function see the MUTEC1 and MUTEC234 pins in Section 4.11.
6.7.2
Channel A Volume = Channel B Volume (Px_A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
7
6
5
432
10
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FILT_SEL
0
0
0
000
00
7
6
5
432
10
INV_B4
INV_A4
INV_B3
INV_A3
INV_B2
INV_A2
INV_B1
INV_A1
0
0
0
000
00
7
6
5
432
10
Reserved
MUTEC
Reserved
P1_A=B
P2_A=B
P3_A=B
P4_A=B
SNGLVOL
0
0
0
000
00



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