DS861PP1

35

CS5346

7.10.1

Clock Error (Bit 3)

Function:

Indicates the occurrence of a clock error condition.

7.10.2

Overflow (Bit 1)

Function:

Indicates the occurrence of an ADC overflow condition.

7.10.3

Underflow (Bit 0)

Function:

Indicates the occurrence of an ADC underflow condition.

7.11

Status Mask - Address 0Eh

Function:

The bits of this register serve as a mask for the Status sources found in the register “Status - Address 0Dh”

on page 34. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status

register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the status

register. The bit positions align with the corresponding bits in the Status register.

7.12

Status Mode MSB - Address 0Fh

7.13

Status Mode LSB - Address 10h

Function:

The two Status Mode registers form a 2-bit code for each Status register function. There are three ways to

update the Status register in accordance with the status condition. In the Rising-Edge Active Mode, the sta-

tus bit becomes active on the arrival of the condition. In the Falling-Edge Active Mode, the status bit be-

comes active on the removal of the condition. In Level-Active Mode, the status bit is active during the

condition.

00 - Rising edge active

01 - Falling edge active

10 - Level active

11 - Reserved

7

6

5

432

10

Reserved

Reserved

Reserved

Reserved

ClkErrM

Reserved

OvflM

UndrflM

7

6

5

432

10

Reserved

Reserved

Reserved

Reserved

ClkErr1

Reserved

Ovfl1

Undrfl1

Reserved

Reserved

Reserved

Reserved

ClkErr0

Reserved

Ovfl0

Undrfl0