3

3633E–DFLASH–10/07

AT26DF321

3.

Block Diagram

4.

Memory Array

To provide the greatest flexibility, the memory array of the AT26DF321 can be erased in four lev-

els of granularity including a full chip erase. In addition, the array has been divided into physical

sectors of uniform size, of which each sector can be individually protected from program and

erase operations. The size of the physical sectors is optimized for both code and data storage

applications, allowing both code and data segments to reside in their own isolated

regions. Figure 4-1 on page 4 illustrates the breakdown of each erase level as well as the break-

down of each physical sector.

Figure 2-1.

8-SOIC Top View

Figure 2-2.

16-SOIC Top View

1

2

3

4

8

7

6

5

CS

SO

WP

GND

VCC

NC

SCK

SI

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

NC

VCC

NC

NC

NC

NC

CS

SO

SCK

SI

NC

NC

NC

NC

GND

WP

FLASH

MEMORY

ARRAY

Y-GATING

CS

SCK

SO

SI

Y-DECODER

X-DECODER

I/O BUFFERS

AND LATCHES

CONTROL AND

PROTECTION LOGIC

SRAM

DATA BUFFER

WP

INTERFACE

CONTROL

AND

LOGIC