AT45DB321D datasheet(21/54 Pages) ATMEL

21 / 54 page

3597J–DFLASH–4/08

AT45DB321D

10.2.2

Reading the Security Register

The Security Register can be read by first asserting the CS pin and then clocking in an opcode

of 77H followed by three dummy bytes. After the last don't care bit has been clocked in, the con-

tent of the Security Register can be clocked out on the SO pins. After the last byte of the

Security Register has been read, additional pulses on the SCK pin will simply result in undefined

data being output on the SO pins.

Deasserting the CS pin will terminate the Read Security Register operation and put the SO pins

into a high-impedance state.

Figure 10-4. Read Security Register

11. Additional Commands

11.1

Main Memory Page to Buffer Transfer

A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start

the operation for the DataFlash standard page size (528 bytes), a 1-byte opcode, 53H for buffer

1 and 55H for buffer 2, must be clocked into the device, followed by three address bytes com-

prised of 1 don’t care bit, 13-page address bit (PA12 - PA0), which specify the page in main

memory that is to be transferred, and 10 don’t care bits. To perform a main memory page to

buffer transfer for the binary page size (512 bytes), the opcode 53H for buffer 1 or 55H for buffer

2, must be clocked into the device followed by three address bytes consisting of 2 don’t care

bits, 13-page address bits (A21 - A9) which specify the page in the main memory that is to be

transferred, and 9 don’t care bits. The CS pin must be low while toggling the SCK pin to load the

opcode and the address bytes from the input pin (SI). The transfer of the page of data from the

main memory to the buffer will begin when the CS pin transitions from a low to a high state. Dur-

ing the transfer of a page of data (t

XFR), the status register can be read or the RDY/BUSY can be

monitored to determine whether the transfer has been completed.

Opcode

Data Byte

n + 1

Data Byte

n + x

Each transition

represents 8 bits

AT45DB321D 데이터시트(PDF) 21 Page - ATMEL Corporation