AT89C5131A-RDTUM datasheet(124/188 Pages) ATMEL

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124

4337K–USB–04/08

AT89C5130A/31A-M

The Endpoint 0 is the Default Control Endpoint and will always be configured in Control type.

• Endpoint direction configuration

For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the EPDIR bit of

the UEPCONX register with the following values:

– IN:EPDIR = 1b

– OUT:EPDIR = 0b

For Control endpoints, the EPDIR bit has no effect.

• Summary of Endpoint Configuration:

Do not forget to select the correct endpoint number in the UEPNUM register before access-

ing to endpoint specific registers.

Table 21-1.

Summary of Endpoint Configuration

• Endpoint FIFO reset

Before using an endpoint, its FIFO will be reset. This action resets the FIFO pointer to its

original value, resets the byte counter of the endpoint (UBYCTLX and UBYCTHX registers),

and resets the data toggle bit (DTGL bit in UEPCONX).

The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the corre-

sponding bit in the UEPRST register.

For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then 0000

0000b in the UEPRST register.

Note that the endpoint reset doesn’t reset the bank number for ping-pong endpoints.

21.3

Read/Write Data FIFO

21.3.1

FIFO Mapping

Depending on the selected endpoint through the UEPNUM register, the UEPDATX register

allows to access the corresponding endpoint data fifo.

Endpoint Configuration

EPEN

EPDIR

EPTYPE

UEPCONX

Disabled

XXb

0XXX XXXb

Control

00b

80h

Bulk-in

10b

86h

Bulk-out

10b

82h

Interrupt-In

11b

87h

Interrupt-Out

11b

83h

Isochronous-In

01b

85h

Isochronous-Out

01b

81h

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