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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ACS8522AT 데이터시트(PDF) 39 Page - Semtech Corporation |
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ACS8522AT 데이터시트(HTML) 39 Page - Semtech Corporation |
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39 / 118 page  ACS8522A SETS LITE ADVANCED COMMS & SENSING FINAL DATASHEET Revision 1.00/September 2007 © Semtech Corp. Page 39 www.semtech.com Figure 12 and Figure 13 show the timing diagrams of read and write accesses for this mode. Figure 12 Read Access Timing for SERIAL Interface Table 18 Read Access Timing for SERIAL Interface (For use with Figure 12) Symbol Parameter MIN TYP MAX tsu1 Setup SDI valid to SCLKrising edge 4 ns - - tsu2 Setup CSBfalling edge to SCLKrising edge 14 ns - - td1 Delay SCLKrising edge (SCLKfalling edge for CLKE = 1) to SDO valid - - 18 ns td2 Delay CSBrising edge to SDO high-Z - - 16 ns tpw1 SCLK Low time 22 ns - - tpw2 SCLK High time 22 ns - - th1 Hold SDI valid after SCLKrising edge 6 ns - - th2 Hold CSB Low after SCLKrising edge, for CLKE = 0 Hold CSB Low after SCLKfalling edge, for CLKE = 1 5 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge)10 ns - - F8526D_013ReadAccSerial_01 SCLK CSB CLKE = 0; SDO data is clocked out on the rising edge of SCLK CLKE = 1; SDO data is clocked out on the falling edge of SCLK R/W Output not driven, pulled low by internal resistor SDI SDO tsu2 tsu1 th1 tpw1 tpw2 _ A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 th2 td2 td1 SCLK CSB R/W Output not driven, pulled low by internal resistor SDI SDO _ A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 th2 td2 td1 |
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