DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers

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Table 1 shows the speed for each class of instruction. Note that many of the instructions have multiple op

codes. There are 255 op codes for 111 instructions. Of the 255 op codes, 159 are three times faster than

the original 80C32. While a system that emphasizes those instructions will see the most improvement, the

large total number that receive a 3 to 1 improvement assure a dramatic speed increase for any system. The

speed improvement summary is provided below.

SPEED ADVANTAGE SUMMARY

#OP CODES

SPEED

IMPROVEMENT

159

3.0 x

51

1.5 x

43

2.0 x

2

2.4 x

255

Average: 2.5

MEMORY ACCESS

The DS80C320/DS80C323 do not contain on-chip ROM and 256 bytes of scratchpad RAM. Off-chip

memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2. Figure 3

shows a typical memory connection. Timing diagrams are provided in the Electrical Specifications

section. Program memory (ROM) is accessed at a fixed rate determined by the crystal frequency and the

actual instructions. As previously mentioned, an instruction cycle requires 4 clocks. Data memory (RAM)

is accessed according to a variable-speed MOVX instruction as described below.

Figure 3. Typical Memory Connection