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POWER MANAGEMENT

SC1189

Layout Guidelines (Cont.)

4) The Output Capacitor(s) (Cout) should be located as

close to the load as possible, fast transient load currents

are supplied by Cout only, and connections between Cout

and the load must be short, wide copper areas to mini-

mize inductance and resistance.

5) The SC1189 is best placed over a quiet ground plane

area, avoid pulse currents in the Cin, Q1, Q2 loop flowing

in this area. PGNDH and PGNDL should be returned to

the ground plane close to the package. The AGND pin

should be connected to the ground side of (one of) the

output capacitor(s). If this is not possible, the AGND pin

may be connected to the ground path between the Output

Capacitor(s) and the Cin, Q1, Q2 loop. Under no circum-

stances should AGND be returned to a ground inside the

Cin, Q1, Q2 loop.

6) Vcc for the SC1189 should be supplied from the 5V

supply through a 10

Ω resistor, the Vcc pin should be

decoupled directly to AGND by a 0.1

µF ceramic capacitor,

trace lengths should be as short as possible.

7) The Current Sense resistor and the divider across it

should form as small a loop as possible, the traces run-

ning back to CS+ and CS- on the SC1189 should run par-

allel and close to each other. The 0.1

µF capacitor should

be mounted as close to the CS+ and CS- pins as possible.

8) Ideally, the grounds for the two LDO sections should be

returned to the ground side of (one of) the output

capacitor(s).

Vout

5V

+

+

Currents in Power Section