11

6201C–PMAAC–31-Jul-07

AT73C239

7.

Startup Procedure

At VBAT Rising:

• LPBG automatically starts up.

• POR1 starts up LDO4.

At VDD3 Rising:

• POR2 enables the following:

– Supply Monitor with shutdown threshold setup at 2.7V in order to prevent corruption

in the baseband chip, when the core is still supplied

– Internal State machine that enables the other circuits according to the diagram

shown in Figure 7-1 on page 12.

– Two Wire Interface

At VDD3 Falling:

• The Supply Monitor generates a shut-down control signal when V

• The State Machine, upon receiving the shut-down control signal, generates the XRESO

signal to set the baseband chip in reset mode.

• The State Machine switches off LDO1, LDO2 and LDO3. HPBG is kept on in order to provide

a fast startup of the LDOs in case of glitches on V