5

LT1055/LT1056

10556fc

For MIL-STD components, please refer to LTC883 data sheet for test

listing and parameters.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Offset voltage is measured under two different conditions:

only, with the chip heated to approximately 38

°C for the LT1055 and to

45

°C for the LT1056, to account for chip temperature rise when the device

is fully warmed up.

Note 3: 10Hz noise voltage density is sample tested on every lot of A

grades. Devices 100% tested at 10Hz are available on request.

Note 4: This parameter is tested on a sample basis only.

Ω swamps

the contribution of current noise.

Note 6: Offset voltage drift with temperature is practically unchanged

when the offset voltage is trimmed to zero with a 100k potentiometer

tighter drift specifications are available on request.

0

LT1055CS8/LT1056CS8

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input Offset Voltage (Note 2)

●

800

2200

µV

Average Temperature Coefficient of Input Offset Voltage

●

415

µV/°C

Input Offset Current

●

18

150

pA

Input Bias Current

●

±60

±400

pA

Large-Signal Voltage Gain

●

60

250

V/mV

CMRR

Common Mode Rejection Ratio

●

82

98

dB

PSRR

Power Supply Rejection Ratio

●

87

103

dB

Output Voltage Swing

●

±12

±13.1

V