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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADNS-6010 데이터시트(PDF) 21 Page - AVAGO TECHNOLOGIES LIMITED |
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ADNS-6010 데이터시트(HTML) 21 Page - AVAGO TECHNOLOGIES LIMITED |
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21 / 52 page  21 State of Signal Pins After VDD is Valid Pin Before Reset During Reset After Reset SPI pullups undefined off on (default) NCS hi-Z control functional hi-Z control functional functional MISO driven or hi-Z (per NCS) driven or hi-Z (per NCS) low or hi-Z (per NCS) SCLK undefined ignored functional MOSI undefined ignored functional XY_LASER undefined hi-Z functional RESET functional high (externally driven) functional NPD undefined ignored functional LASER_NEN undefined high (off) functional State of Signal Pins During Power Down Pin NPD low After wake from PD SPI pullups off pre-PD state NCS hi-Z control functional functional MISO low or hi-Z (per NCS) pre-PD state or hi-Z SCLK ignored functional MOSI ignored functional XY_LASER high (off) functional RESET functional functional NPD low (driven externally) functional REFC VDD3 REFC OSC_IN low OSC_IN OSC_OUT high OSC_OUT LASER_NEN high (off) functional Reset Circuit The ADNS-6010 does not perform an internal power up self-reset; the reset pin must be raised and lowered to reset the chip. This should be done every time power is applied. During power-up there will be a period of time after the power supply is high but before any clocks are available. The table below shows the state of the various pins during power-up and reset when the RESET pin is driven high by a micro-controller. Notes on Power-up and the serial port Power Down Circuit The following table lists the pin states during power down. The chip is put into the power down (PD) mode by low- ering the NPD input. When in PD mode, the oscillator is stopped but all register contents are retained. To achieve the lowest current state, all inputs must be held exter- nally within 200mV of a rail, either ground or VDD3. The chip outputs are driven low or hi-Z during PD to prevent current consumption by an external load. |
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