12

LT1640AL/LT1640AH

The new threshold voltage when the input moves from low

to high is:

VV

R

R

RR

RR

RR

UV LH

UVH

,

•••

•

=

++









2

3

13

12

23

The new threshold voltage when the input moves from

high to low is:

VV

R

R

RR

RR

RR

V

R

R

UV HL

UVL

GATE

,

•••

•

–•

=

++

















2

3

13

12

23

1

3

The new hysteresis value will be:

VV

R

R

RR

RR

RR

V

R

R

HYS

UVHY

GATE

=

++









+









2

3

13

12

23

1

3

•••

•

•

(from low to high) and 37.6V (from high to low). The

hysteresis is 5.4V. A separate resistor divider should be

used to set the overvoltage threshold given by:

VV

RR

R

OV

OVH

=

+









45

5

overvoltage threshold will be 71V.

PWRGD/PWRGD Output

The PWRGD/PWRGD output can be used to directly en-

able a power module when the input voltage to the module

is within tolerance. The LT1640AL has a PWRGD output

for modules with an active low enable input, and the

LT1640AH has a PWRGD output for modules with an

active high enable input.

When the DRAIN voltage of the LT1640AH is high with

turned off and R7 and Q2 clamp the PWRGD pin one diode

drop (

≈0.7V) above the DRAIN pin. Transistor Q2 sinks

the module’s pull-up current and the module turns off.

shorting the bottom of R7 to DRAIN and turning Q2 off.

The pull-up current in the module then flows through R7,

pulling the PWRGD pin high and enabling the module.

+

LT1640AH

SENSE

C1

C3

Q1

R2

R3

C2

R4

R5

R6

R1

4

3

2

OV

GND

– 48V

UV

56

8

1

7

GATE

1640A F11

PWRGD

DRAIN

R7

6.5k

Q2

–

+

Q3

ACTIVE HIGH

ENABLE MODULE

+

–

+

–

ON/OFF

GND

(SHORT PIN)

*

* DIODES INC. SMAT70A

4

3

2

1

+

–

Figure 11. Active High Enable Module

APPLICATIO S I FOR ATIO