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HV430 데이터시트(PDF) 3 Page - Supertex, Inc

부품명 HV430
상세설명  High Voltage Ring Generator
PDF  8 Pages
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제조업체  SUTEX [Supertex, Inc]
홈페이지  http://www.supertex.com
Logo SUTEX - Supertex, Inc

HV430 데이터시트(HTML) 3 Page - Supertex, Inc

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3
Negative High Voltage Output
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
VNgate
Output voltage swing
VNN2
VNN1
V
No load on VNgate
RsourceN
VNgate source resistance
15.0
Ω
IOUT=80mA
RsinkN
VNgate sink resistance
15.0
Ω
IOUT=-80mA
triseN
VNgate rise time
50
ns
Cload=1.0nF
tfallN
VNgate fall time
50
ns
Cload=1.0nF
tpwn(min)
VNgate minimum pulse width
(internally limited)
100
150
200
ns
tdelayN
NIN to VNgate delay time
300
ns
mode=1
VNsen
VNgate current sense voltage
VNN1+0.85
VNN1+1.0
VNN1+1.15
V
tshortN
VNgate current sense OFF time
150
ns
Control Circuitry
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
VIL
Logic input low voltage
0
0.60
V
VDD=5.0V
VIH
Logic input high voltage
2.7
5.0
V
VDD=5.0V
IINdn
Input pull-down current
0.5
1
5
µAPIN, NIN, ENABLE
Rup
Input pull-up resistance
100
200
300
kΩ
MODE
VOL
Logic output low voltage
0.50
V
VDD=5.0V, IOUT=-0.5mA
VOH
Logic output high voltage
4.50
V
VDD=5.0V, IOUT=0.5mA
VRST(OFF)
Reset voltage, device off
3.2
3.5
V
VDD=5.0V
VRST(ON)
Reset voltage, device on
3.7
4.0
V
VDD=5.0V
VRST(HYS)
Reset hysteresis voltage
0.3
V
VDD=5.0V
Ireset
Reset pull-up current
7
10
13
µAVRESET=0-4.5V
tRST(ON)
RESET on delay
1.0
µs
tRST(OFF)
RESET off delay
1.0
µs
tEN(ON)
ENABLE on delay
50
100
150
µs
tEN(OFF)
ENABLE off delay
1.0
µs
tFLT(HOLD)
FAULT hold time
4
NIN/PIN
ENABLE=1
cycles
tDB
Deadband time
35
50
70
ns
Mode=0, Rdb=5.6kΩ
105
140
175
ns
Mode=0, Rdb=18kΩ
tdelay(N-P)
N-off to P-on transistion delay
300
ns
Mode=0, Rdb<27kΩ
tdelay(P-N)
P-off to N-on transistion delay
300
ns
Mode=0, Rdb<27kΩ
∆tdelay(N-P)
Delay difference
-80
0
80
ns
Mode=1
tdelayN(off) - tdelayP(on)
∆tdelay(P-N)
Delay difference
-80
0
80
ns
Mode=1
tdelayP(off) - tdelayN(on)
HV430



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