4

Polarity

Blanking

Latch Enable

Data Input

Clock

Data Out

32-Bit

Shift

Register

(Outputs 3 to 30

not shown)

Latch

Latch

Latch

Latch

Functional Block Diagram

HV4530//HV4630

Function Table

Inputs

Outputs

Function

Shift Reg

HV Outputs

Data Out

12…32

1

2…32

*

All on

X

X

X

L

L

*

*…*ON

ON…ON

*

All off

X

X

X

L

H

*

*…*

OFF OFF…OFF

*

Invert mode

X

X

L

H

L

*

*…***…**

Load S/R

H or L

↓

LH

H

H or L *…***…**

XH or L

↑

HH

*

*…***…**

XH or L

↑

HL

*

*…***…**

L

↓

HH

H

L

*…*

OFF

*…**

H

↓

H

HHH

*…*ON*…**

Notes:

H = high level = -12V, L = low level = 0V, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transition.

* = dependent on previous stage’s state before the last CLK high-to-low transition or last LE high.

Data

CLK

LE

BL

POL

Load

latches

Transparent

latch mode