CoreDES

4

v4.0

CoreDES Device Requirements

The CoreDES macro has been implemented in several of the Actel device families. A summary of the implementation

data is listed in Table 1.

Data throughput is computed by taking the bit width of the data (64 bits), dividing by the number of cycles (16), and

multiplying by the clock rate (performance); the result is listed in Mbps (millions of bits per second).

CoreDES Verification

The comprehensive simulation testbench (included with

Netlist and RTL versions of the core) verifies the CoreDES

macro against several of the tests listed in NIST Special

Publication 800-17, Modes of Operation Validation

System (MOVS): Requirements and Procedures. The

testbench applies several tests to the CoreDES macro,

including: sample round output tests, variable plaintext

tests, variable cipher key tests, permutation operation

tests, and substitution table tests. Using the supplied

testbench as a guide, the user can easily customize the

verification of the core by adding or removing any of the

tests listed in NIST Special Publication 800-17 or by

adding any custom test cases.

Table 1 • CoreDes Device Utilization and Performance

Family

Cells or Tiles

Utilization

Performance

Throughput

Sequential

Combinatorial

Total

Device

Total

Fusion

148

1123

1271

AFS600

10%

80 MHz

320 Mbps

ProASIC3/E

148

1123

1271

A3PE600-2

10%

80 MHz

320 Mbps

142

1328

1470

APA075-STD

48%

50 MHz

200 Mbps

Axcelerator

141

601

742

AX125-3

37%

125 MHz

500 Mbps

RTAX-S

141

601

742

RTAX1000S-1

4%

74 MHz

296 Mbps

SX-A

141

628

769

A54SX16A-3

53%

100 MHz

400 Mbps

RTSX-S

141

628

769

RT54SX32S-2

27%

55 MHz

220 Mbps

Note:

Data in this table achieved using typical synthesis and layout settings.