EX128-CS100 datasheet(21/44 Pages) ACTEL

21 / 44 page

eX Automotive Family FPGAs

v3.2

1-17

eX Timing Model

Hardwired Clock

External Setup =

tINYH + tIRD1 + tSUD – tHCKH

1.3 + 0.5 + 0.8 – 1.8 = 0.8 ns

Clock-to-Out (Pad-to-Pad), typical

=tHCKH + tRCO + tRD1 + tDHL

1.8 + 1.0 + 0.6 + 4.9 = 8.3 ns

Routed Clock

External Setup =

tINYH + tIRD2 + tSUD – tRCKH

1.3 + 0.7 + 0.8 – 2.3 = 0.5 ns

Clock-to-Out (Pad-to-Pad), typical

=tRCKH + tRCO + tRD1 + tDHL

2.3 + 1.0 + 0.6 + 4.9 = 8.8 ns

Note: *Values shown for eX128, worst-case automotive conditions (2.3 V VCCA, 3.3 V VCCI, 35 pF Pad Load).

Figure 1-15 • eX Timing Model

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

INYH = 1.3 ns

IRD2 = 0.7 ns

IRD1 = 0.5 ns

Combinatorial

Cell

I/O Module

DHL = 4.9 ns

RD8 = 1.9 ns

RD4 = 1.1 ns

RD1 = 0.6 ns

PD = 1.1 ns

I/O Module

DHL = 4.9 ns

RD1 = 0.6 ns

RCO= 1.0 ns

I/O Module

INYH = 1.3 ns

ENZL= 4.0 ns

SUD = 0.8 ns

HD = 0.0 ns

SUD = 0.8 ns

HD = 0.0 ns

RCKH= 2.3 ns

(100% Load)

IRD1 = 0.5 ns

Cell

Routed

Clock

RD1 = 0.6 ns

RCO= 1.0 ns

HCKH= 1.8 ns

Cell

Hardwired

Clock

I/O Module

DHL = 4.9 ns

ENZL= 4.0 ns

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