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A32100DX-FPLC 데이터시트(PDF) 47 Page - Actel Corporation

부품명 A32100DX-FPLC
상세설명  Integrator Series FPGAs: 1200XL and 3200DX Families
PDF  84 Pages
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제조업체  ACTEL [Actel Corporation]
홈페이지  http://www.actel.com
Logo ACTEL - Actel Corporation

A32100DX-FPLC 데이터시트(HTML) 47 Page - Actel Corporation

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Discontinued – v3.0
47
Integrato r Se ries F P G A s: 1200 XL and 320 0DX Fam ilies
A322 00DX Timing Char act eristics
(Worst-Case Commercial Conditions VCC = 4.75 V, TJ = 70°C)
‘–3 Speed
‘–2 Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
3.3V ‘Std’
Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays
Combinatorial Functions
tPD
Internal Array Module Delay
2.0
2.4
2.7
3.2
4.5
3.7
ns
tPDD
Internal Decode Module Delay
2.5
2.9
3.3
3.9
5.6
4.5
ns
Predicted Module Routing Delays
tRD1
FO=1 Routing Delay
1.1
1.35
1.5
1.8
2.6
2.1
ns
tRD2
FO=2 Routing Delay
1.7
2.0
2.2
2.6
3.7
3.0
ns
tRD3
FO=3 Routing Delay
2.1
2.4
2.8
3.3
4.7
3.8
ns
tRD4
FO=4 Routing Delay
2.6
3.0
3.4
4.0
5.7
4.7
ns
tRD5
FO=8 Routing Delay
4.5
5.3
6.0
7.0
10.0
8.2
ns
tRDD
Decode-to-Output Routing Delay
0.6
0.67
0.8
0.9
1.3
1.0
ns
Sequential Timing Characteristics
tCO
Flip-Flop Clock-to-Output
2.3
2.7
3.1
3.6
5.1
4.2
ns
tGO
Latch Gate-to-Output
2.0
2.4
2.7
3.2
4.5
3.7
ns
tSU
Flip-Flop (Latch) Set-Up Time
0.3
0.35
0.4
0.47
0.7
0.55
ns
tH
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset to Output
2.3
2.7
3.1
3.6
5.1
4.2
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.75
0.9
1.0
1.4
1.17
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.1
3.7
4.2
4.9
7.0
5.7
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
4.1
4.9
5.5
6.5
9.2
7.6
ns



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