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AX2000-1CS896PP 데이터시트(PDF) 93 Page - Actel Corporation

부품명 AX2000-1CS896PP
상세설명  Axcelerator Family FPGAs
PDF  226 Pages
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제조업체  ACTEL [Actel Corporation]
홈페이지  http://www.actel.com
Logo ACTEL - Actel Corporation

AX2000-1CS896PP 데이터시트(HTML) 93 Page - Actel Corporation

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Axcelerator Family FPGAs
v2.7
2-79
Table 2-92 • Sixteen RAM Blocks Cascaded
Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C
'–2' Speed
'–1' Speed
'Std' Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
Write Mode
tWDASU
Write Data Setup vs. WCLK
16.54
18.84
22.15
ns
tWDAHD
Write Data Hold vs. WCLK
0.22
0.25
0.3
ns
tWADSU
Write Address Setup vs. WCLK
16.54
18.84
22.15
ns
tWADHD
Write Address Hold vs. WCLK
0.22
0.25
0.3
ns
tWENSU
Write Enable Setup vs. WCLK
16.54
18.84
22.15
ns
tWENHD
Write Enable Hold vs. WCLK
0.22
0.25
0.3
ns
tWCKH
WCLK Minimum High Pulse Width
0.98
1.11
1.31
ns
tWCLK
WCLK Minimum Low Pulse Width
17.44
19.86
23.35
ns
tWCKP
WCLK Minimum Period
34.87
39.73
46.7
ns
Read Mode
tRADSU
Read Address Setup vs. RCLK
18.13
20.65
24.27
ns
tRADHD
Read Address Hold vs. RCLK
0.00
0.00
0.00
ns
tRENSU
Read Enable Setup vs. RCLK
18.13
20.65
24.27
ns
tRENHD
Read Enable Hold vs. RCLK
0.00
0.00
0.00
ns
tRCK2RD1
RCLK-To-OUT (Pipelined)
12.71
14.48
17.03
ns
tRCK2RD2
RCLK-To-OUT (Non-Pipelined)
13.91
15.85
18.63
ns
tRCLKH
RCLK Minimum High Pulse Width
0.95
1.08
1.27
ns
tRCLKL
RCLK Minimum Low Pulse Width
18.75
21.36
25.11
ns
tRCKP
RCLK Minimum Period
37.5
42.72
50.22
ns



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