AX2000-1CS896B datasheet(74/226 Pages) ACTEL

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AX2000-1CS896B 데이터시트(PDF) 74 Page - Actel Corporation

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Axcelerator Family FPGAs

2- 60

v2.7

The ClockTileDist Cluster contains an HCLKMux (HM)

module for each of the four HCLK trees and a CLKMux

(CM) module for each of the CLK trees. The HCLK

branches then propagate horizontally through the

middle of the core tile to HCLKColDist (HD) modules in

every SuperCluster column. The CLK branches propagate

vertically through the center of the core tile to

CLKRowDist (RD) modules in every SuperCluster row.

Together, the HCLK and CLK branches provide for a low-

skew global fanout within the core tile (Figure 2-40 and

Figure 2-41).

Figure 2-40 • CTD, CD, and HD Module Layout

Figure 2-41 • HCLK and CLK Distribution within a Core Tile

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