5

LTC1402

Note 13: If less than 7.3ns is allowed, the output data will appear one

clock cycle later. It is best for CONV to rise half a clock before SCK, when

running the clock at rated speed.

Note 14: Not the same as aperture delay. Aperture delay is smaller (2.6ns)

because the 0.8ns delay through the sample-and-hold is subtracted from

the CONV to Hold mode delay.

Note 15: The rising edge of SCK is guaranteed to catch the data coming

out into a storage latch.

ELECTRICAL CHARACTERISTICS

Note 16: The time period for acquiring the input signal is started by the

14th rising clock and it is ended by the rising edge of convert.

Note 17: The internal reference settles in 2ms after it wakes up from Sleep

mode with one or more cycles at SCK and a 10

µF capacitive load. The

wake up. This ensures valid REFREADY bit operation even with higher load

Note 18: The full power bandwidth is the frequency where the output code

TYPICAL PERFOR A CE CHARACTERISTICS

ENOBs and SINAD

vs Input Frequency (Bipolar)

SNR vs Input Frequency (Bipolar)

ENOBs and SINAD

vs Input Frequency (Unipolar)

SNR vs Input Frequency (Unipolar)

(Bipolar Mode Plots Run with Dual

±5V Supplies.

INPUT FREQUENCY (Hz)

4

6

8

1401 G01

2

0

12

10

3

5

7

1

11

9

26

38

50

14

2

74

62

20

32

44

8

68

56

INPUT FREQUENCY (Hz)

–80

–60

–40

1401 G02

–100

–120

0

–20

–90

–70

–50

–110

–10

–30

THD

SFDR

2ND

3RD

INPUT FREQUENCY (Hz)

–50

–38

–26

1401 G03

–62

–74

–2

–14

–56

–44

–32

–68

–8

–20

INPUT FREQUENCY (Hz)

4

6

8

1401 G04

2

0

12

10

3

5

7

1

11

9

26

38

50

14

2

74

62

20

32

44

8

68

56

INPUT FREQUENCY (Hz)

–80

–60

–40

1401 G05

–100

–120

0

–20

–90

–70

–50

–110

–10

–30

THD

SFDR

2ND

3RD

INPUT FREQUENCY (Hz)

–50

–38

–26

1401 G06

–62

–74

–2

–14

–56

–44

–32

–68

–8

–20

5 Harmonic THD, 2nd, 3rd and

SFDR vs Input Frequency

(Bipolar)

5 Harmonic THD, 2nd, 3rd and

SFDR vs Input Frequency

(Unipolar)