5

LTC1502-3.3

TEST CIRCUIT

Regulator Operation

The LTC1502-3.3 uses a quadrupler charge pump DC/DC

converter to produce a boosted output voltage. The

quadrupler charge pump consists of two voltage doubler

charge pumps (CP1 and CP2 on the Block Diagram)

the CP1 output voltage is stored on external capacitor C2.

The C2 pin also serves as the input for doubler CP2 whose

doubler is controlled by a two-phase clock which is

generated in the Timing Control circuit. On phase one of

the clock, the flying capacitors C1 and C3 are charged to

their respective input voltages. On phase two each charged

flying capacitor is stacked on top of the input voltage and

discharged through an internal switch onto its respective

output. This sequence of charging and discharging the

CP1 and CP2 flying capacitors continues at the free

running oscillator frequency (500kHz typ) until the output

is in regulation.

Regulation is achieved by comparing the divided down

output voltage to a fixed voltage reference. The charge

pump clocks are disabled when the output voltage is

above the desired regulation point set by COMP1. When

the output has dropped below the lower trip point of

COMP1, the charge pump clocks are turned back on until

Enhanced Start-Up

Enhanced start-up capability is provided by the COMP2

circuitry. COMP2 compares the divided down C2 voltage

output charge pump CP2 whenever the divided C2 voltage

high impedance state until the voltage on C2 has been

proper start-up). This allows a higher internal gate drive

voltage to be generated (from the C2 pin) before the output

prevent a lockup condition if C2 droops too low during

start-up. By the time the output nears the regulation point,

the C2 voltage is well above the lower trip point of COMP2

and CP2 will remain enabled. This method of disabling the

output charge pump while an internal boosted gate drive

supply is developed allows the part to start up at low

voltages with a larger output current load than would

otherwise be possible.

Shutdown

Shutdown is implemented using an external pull-down

pull-down device is an open-drain FET with resistive cur-

rent limiting (see Figure 1). The pull-down device must sink

up to 300

µA and pull down below 0.2V to ensure proper

shutdown operation, however, the actual series resistance

is not critical. The pull-down device must also go into a Hi-

Z state for the LTC1502-3.3 to become active.

The timing control circuitry forces the CP1 switches into

a high impedance state every 16 clock cycles. The Hi-Z

duration is equal to one clock cycle. At the end of the

low state, the part will go into shutdown mode. When the

pull-down device is disabled, an internal pull-up current

1

2

3

1502-3.3 TC

4

8

7

1

µF

100

Ω

6

5

GND

100pF

SWITCH

CLOSED FOR

SHUTDOWN

1

µF

10

µF

10

µF

10

µF

LTC1502-3.3

C2