LTC2420CS8 datasheet(21/36 Pages) LINER

21 / 36 page

LTC2420

APPLICATIO S I FOR ATIO

capacitor tied to CS, see Figure 12. The time the converter

spends in the sleep state is determined by the value of the

external timing capacitor, see Figures 13 and 14. Once the

voltage at CS falls below an internal threshold (

≈1.4V), the

device automatically begins outputting data. The data

output cycle begins on the first rising edge of SCK and

ends on the 24th rising edge. Data is shifted out the SDO

pin on each falling edge of SCK. The internally generated

serial clock is output to the SCK pin. This signal may be

used to shift the conversion result into external circuitry.

After the 24th rising edge, CS is pulled HIGH and a new

conversion is immediately started. This is useful in appli-

cations requiring periodic monitoring and ultralow power.

Figure 15 shows the average supply current as a function

of capacitance on CS.

It should be noticed that the external capacitor discharge

current is kept very small in order to decrease the con-

verter power dissipation in the sleep state. In the autostart

mode the analog voltage on the CS pin cannot be observed

without disturbing the converter operation using a regular

oscilloscope probe. When using this configuration, it is

important to minimize the external leakage current at the

CS pin by using a low leakage external capacitor and

properly cleaning the PCB surface.

SDO

Hi-Z

SCK

(INTERNAL)

VCC

GND

2420 F12

VCC

VREF

SCK

VIN

SDO

GND

CEXT

VREF

0.1V TO VCC

VIN

–0.12VREF TO 1.12VREF

µF

2.7V TO 5.5V

LTC2420

BIT 0

SIG

BIT 21

BIT 22

SLEEP

DATA OUTPUT

CONVERSION

EOC

BIT 23

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

VCC

Figure 12. Internal Serial Clock, Autostart Operation

CAPACITANCE ON CS (pF)

1000

10000

2420 F13

100

100000

VCC = 5V

VCC = 3V

Figure 13. CS Capacitance vs fSAMPLE

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