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LTC3524 데이터시트(PDF) 13 Page - Linear Technology |
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LTC3524 데이터시트(HTML) 13 Page - Linear Technology |
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13 / 16 page ![]() LTC3524 13 3524f and VH should be at least 0.47μF. Please be certain that the capacitors used are rated for the maximum voltage with adequate safety margin. Refer to Table 2 for a listing of capacitor vendors. Table 2. Capacitor Vendor Information Supplier Phone Website AVX (803) 448-9411 www.avxcorp.com Murata (714) 852-2001 www.murata.com Samsung (408) 544-5200 www.sem.samsung.com Taiyo Yuden (800) 368-2496 www.t-yuden.com TDK (847) 803-6100 www.component.tdk.com APPLICATIONS INFORMATION Figure 4. Suggested Layout Two Layer Board (Not to Scale) Printed Circuit Board Layout Guidelines High-speed operation of the LTC3524 demands care- ful attention to PCB layout. You will not get advertised performance with a careless layout. Figure 4 shows the recommended component placement for a double layer PCB. The bottom layer is used as a common ground plane except for the VN trace. VOUT LAYOUT NOTES: *KEEP RPROG AWAY FROM SW2 TRACES LIGHT GREY TOP LAYER VIA TO BOTTOM GROUND PLANE. GROUND PLANE FILLS BOTTOM VIN VN COMPONENT AND IC SIZES NOT TO SCALE TOP VIEW 24 23 22 21 20 19 7 8 9 10 11 12 6 5 1 13 14 15 16 17 18 LED2 CH – CH + VH FBH FBN ELED1 PROG ELED2 SW2 VLED LED1 * L2 ELED1 ELED2 ELCD R1 VH GND GND GND WHITE LEDs SCHOTTKY DIODE WHITE LEDs 4 3 2 C2+ V2x VNIN CN+ NC VN ELCD VIN FBVO VOUT SW1 C2– L1 3524 F04 SCHOTTKY DIODE |
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