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LTC4088-1/LTC4088-2

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Battery Charger Stability Considerations

The LTC4088-1/LTC4088-2’s battery charger contains both

a constant-voltage and a constant-current control loop. The

constant-voltage loop is stable without any compensation

when a battery is connected with low impedance leads.

Excessive lead length, however, may add enough series

inductance to require a bypass capacitor of at least 1µF

from BAT to GND.

High value, low ESR multilayer ceramic chip capacitors

reduce the constant-voltage loop phase margin, possibly

resulting in instability. Ceramic capacitors up to 22µF may

be used in parallel with a battery, but larger ceramics should

be decoupled with 0.2

Ω to 1Ω of series resistance.

Furthermore, a 4.7µF capacitor in series with a 0.2

Ω to 1Ω

resistor from BAT to GND is required to prevent oscillation

when the battery is disconnected.

In constant-current mode, the PROG pin is in the feed-

back loop rather than the battery voltage. Because of the

additional pole created by any PROG pin capacitance,

capacitance on this pin must be kept to a minimum. With

no additional capacitance on the PROG pin, the charger

is stable with program resistor values as high as 25k.

However, additional capacitance on this node reduces the

maximum allowed program resistor. The pole frequency at

the PROG pin should be kept above 100kHz. Therefore, if

the PROG pin has a parasitic capacitance, CPROG, the fol-

lowing equation should be used to calculate the maximum

resistance value for RPROG:

kHz C

PROG

≤

100

π ••

APPLICATIO S I FOR ATIO

LTC4088-2 데이터시트(PDF) 21 Page - Linear Technology