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PLDM7-G 2001-01

FAST/TTL 3-Bit Schematic

5

7

Vcc

OUT

8

16

10

9

E

P1

GND

P3

P2

Output

Buffer

11

4

IN

Delay Line

3-Bit Programmable

Dimensions in Inches (mm)

3-Bit Programmable Delay Modules

PLDM7 Series FAST/TTL Logic

7 Delay Steps -- 7 ns Inherent Delay

Available in Surface Mount

25

MAX.

.260

(6.60)

TYP.

.810

(20.57)

.300

(7.62)

MAX.

.100

(2.54)

TYP.

.050

(1.27)

TYP.

.020

(0.51)

TYP.

.120

(3.05)

MIN.

.300

(7.62)

.400

(10.16)

MAX.

.010

(0.25)

TYP.

16-Pin SMD Pkg. Unused leads are NOT removed.

To Specify SMD Package, Add "G" Suffix to P/N

Examples: PLDM7-1.25G, PLDM7-2G

.100

(2.54)

TYP.

.040

(1.02)

TYP.

.020

(0.51)

TYP.

.510 (12.95)

.480 (12.19)

.025

(0.64)

.400

(10.16)

1.02

(25.9)

MAX.

.010

(0.25)

TYP.

.285

(7.24)

MAX.

.015

(0.38)

3-Bit TTL

Part Number

Delay per

Step (ns)

Error ref.

to 000

(ns)

Initial

Delay (ns)

Referenced to "000" - Delay (ns) per Program Setting (P3*P2*P1)

000

000

001

010

011

100

101

110

111

PLDM7-1

1.0 ± .4

± .50

7 ± 1.0

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

PLDM7-1.2

1.2 ± .4

± .60

7 ± 1.0

0.0

1.2

2.4

3.6

4.8

6.0

7.2

8.4

PLDM7-1.25

1.25 ± .5

± .70

7 ± 1.0

0.0

1.25

2.5

3.75

5.0

6.25

7.5

8.75

PLDM7-1.3

1.3 ± .5

± .70

7 ± 1.0

0.0

1.3

2.6

3.9

5.2

6.5

7.8

9.1

PLDM7-1.5

1.5 ± .5

± .70

7 ± 1.0

0.0

1.5

3.0

4.5

6.0

7.5

9.0

10.5

PLDM7-1.8

1.8 ± .6

± .80

7 ± 1.0

0.0

1.8

3.6

5.4

7.2

9.0

10.8

12.6

PLDM7-1.9

1.9 ± .7

± .80

7 ± 1.0

0.0

1.9

3.8

5.7

7.6

9.5

11.4

13.3

PLDM7-2

2.0 ± .7

± .80

7 ± 1.0

0.0

2.0

4.0

6.0

8.0

10.0

12.0

14.0

PLDM7-2.5

2.5 ± .7

± .90

7 ± 1.0

0.0

2.5

5.0

7.5

10.0

12.5

15.0

17.5

PLDM7-2.6

2.6 ± .7

± .90

7 ± 1.0

0.0

2.6

5.2

7.8

10.4

13.0

15.6

18.2

PLDM7-3

3.0 ± .7

± 1.0

7 ± 1.0

0.0

3.0

6.0

9.0

12.0

15.0

18.0

21.0

PLDM7-5

5.0 ± 1.0

± 1.5

7 ± 1.0

0.0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

PLDM7-8

8.0 ± 1.2

± 2.5

7 ± 1.0

0.0

8.0

16.0

24.0

32.0

40.0

48.0

56.0

PLDM7-10

10.0 ± 1.5

± 3.0

7 ± 1.0

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

_

ENABLE input (Pin 7) is active low. Output will be disabled ( low) when " E " is high.

INPUT FAN-IN: Input, pin 4, is loaded by the internal passive

network and 8 gate inputs (74S type). The source driving Pin 4

should be FAST/TTL (74S/74F) type or equivalent, and should not

be used to drive any load other than the delay line input.

V

5.00VDC

Input Pulse Voltage ................................................... 3.20V

Input Pulse Rise Time ....................................... 3.0 ns max.

Input Pulse Width / Period ........................... 1000 / 2000 ns

2. Delay Times measured at 1.50V level of leading edge.

3. Rise Times measured from 0.75V to 2.40V.

4. 10pf probe and fixture load on output.

CUMULATIVE TOLERANCES: "Error" Tolerance is for Programmed Delays referenced to Initial Delay, Setting "000."

For example, the setting "111" delay of PLDM7-10 is 70.0

± 3.0ns ref. to "000," and 77.0 ± 4.0ns referenced to the input.

OPERATING SPECIFICATIONS

V

5.00 ± 0.25 VDC

I

CC

Supply Current ......................... 60 mA typ., 80 mA max

Logic “1” Input *: V

I

Logic “0” Input *: V

0.80 V max.

I

-2.0 mA mA

V

OH

Logic “1” Voltage Out .................................. 2.40 V min.

V

OL

Logic “0” Voltage Out ............................... 0.50 V max.

P

WI

Input Pulse Width ............................. 40% of Delay min.

* Refer to "INPUT FAN-IN" note above.

IIL/IIH specified for Programming pins 9, 10 & 11.