S25FL032P datasheet(21/64 Pages) SPANSION

21 / 64 page

February 12, 2009 S25FL032P_00_02

S25FL032P

Data

Sheet

(Preliminar y )

Command Definitions

The host system must shift all commands, addresses, and data in and out of the device, beginning with the

most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts the one-byte

command on SI (all commands are one byte long), most significant bit first. Each successive bit is latched on

the rising edge of SCK. Table 9.1 lists the complete set of commands.

Every command sequence begins with a one-byte command code. The command may be followed by

address, data, both, or nothing, depending on the command. CS# must be driven high after the last bit of the

command sequence has been written.

The Read Data Bytes (READ), Read Data Bytes at Higher Speed (FAST_READ), Dual Output Read (DOR),

Quad Output Read (QOR), Dual I/O High Performance Read (DIOR), Quad I/O High Performance Read

(QIOR), Read Status Register (RDSR), Read Configuration Register (RCR), Read OTP Data (OTPR), Read

Manufacturer and Device ID (READ_ID), Read Identification (RDID) and Release from Deep Power-Down

and Read Electronic Signature (RES) command sequences are followed by a data output sequence on SO.

CS# can be driven high after any bit of the sequence is output to terminate the operation.

The Page Program (PP), Quad Page Program (QPP), 64 KB Sector Erase (SE), 4 KB Parameter Sector

Erase (P4E), 8 KB Parameter Sector Erase (P8E), Bulk Erase (BE), Write Status and Configuration Registers

(WRR), Program OTP space (OTPP), Write Enable (WREN), or Write Disable (WRDI) commands require that

CS# be driven high at a byte boundary, otherwise the command is not executed. Since a byte is composed of

eight bits, CS# must therefore be driven high when the number of clock pulses after CS# is driven low is an

exact multiple of eight.

The device ignores any attempt to access the memory array during a Write Registers, program, or erase

operation, and continues the operation uninterrupted.

The instruction set is listed in Table 9.1.

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