CDCR81

DIRECT RAMBUS

™ CLOCK GENERATOR

SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999

3

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

CLK

20

O

Output clock

CLKB

18

O

Output clock (complement)

GNDC

8

GND for phase aligner

GNDI

5

GND for control inputs

GNDO

17, 21

GND for clock outputs

GNDP

4

GND for PLL

MULT0

15

I

PLL multiplier select

MULT1

14

I

PLL multiplier select

NC

19

Not used

PCLKM

6

I

Phase detector input

PWRDNB

12

I

Active low power down

REFCLK

2

I

Reference clock

S0

24

I

Mode control

S1

23

I

Mode control

S2

13

I

Mode control

STOPB

11

I

Active low output disable

SYNCLKN

7

I

Phase detector input

VDDC

9

VDD for phase aligner

VDDIPD

10

Reference voltage for phase detector inputs and STOPB

VDDIR

1

Reference voltage for REFCLK

VDDO

16, 22

VDD for clock outputs

VDDP

3

VDD for PLL