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HC1S25 데이터시트(PDF) 11 Page - Altera Corporation |
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HC1S25 데이터시트(HTML) 11 Page - Altera Corporation |
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11 / 110 page ![]() Altera Corporation 2–5 September 2008 Description, Architecture, and Features Although memory resource implementation is equivalent, the number of specific M-RAM blocks are not necessarily the same between corresponding Stratix and HardCopy Stratix devices. Table 2–3 shows the number of M-RAM blocks available in each device. In HardCopy Stratix devices, it is not possible to preload RAM contents using a MIF after powering up; the output registers of memory blocks will have unknown values. This occurs because there is no configuration process that is executed. 1 Violating the setup or hold time requirements on address registers could corrupt the memory contents. This requirement applies to both read and write operations. Table 2–4 illustrates the differences between HardCopy Stratix and Stratix memory. Table 2–3. HardCopy Stratix and Stratix M-RAM Block Comparison HardCopy Stratix Stratix Device M-RAM Blocks Device M-RAM Blocks HC1S25 2 EP1S25 2 HC1S30 2 EP1S30 4 HC1S40 2 EP1S40 4 HC1S60 6 EP1S60 6 HC1S830 6 EP1S830 9 Table 2–4. HardCopy Stratix and Stratix Memory Comparison HardCopy Stratix Stratix HC1S30 and HC1S40 devices have two M-RAM blocks. HC1S80 devices have six M-RAM blocks. EP1S30 and EP1S40 devices have four M-RAM blocks. EP1S80 devices have nine M-RAM blocks. It is not possible to initialize M512 and M4k RAM contents during power-up. The contents of M512 and M4K RAM blocks can be preloaded during configuration with data specified in a MIF. The contents of memory output registers are unknown after POR. The contents of memory output registers are initialized to ‘0’ after POR. |
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