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ZADCS1222 데이터시트(PDF) 7 Page - Zentrum Mikroelektronik Dresden AG |
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ZADCS1222 데이터시트(HTML) 7 Page - Zentrum Mikroelektronik Dresden AG |
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7 / 21 page ![]() Datasheet ZADCS1282/1242/1222 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. 7/21 1.5 Electrical Characteristics 1.5.1 General Parameters (VDD = +2.7V to + 5.25V; fSCLK = 3.2MHz (50% duty cycle); 16 clocks/conversion cycle (200 ksps); VREF = 2.500V applied to VREF pin; qOP = qOPmin … qOPmax) Parameter Symbol Conditions Min Typ Max Unit DC Accuracy Resolution 12 Bits Relative Accuracy ZADCS1282 / ZADCS1282V ZADCS1242 / ZADCS1242V ZADCS1222 / ZADCS1222V ± 1.0 LSB No Missing Codes NMC 12 Bits Differential Nonlinearity ZADCS1282 / ZADCS1282V ZADCS1242 / ZADCS1242V ZADCS1222 / ZADCS1222V ± 1.0 LSB Offset Error ± 0.5 ± 3.0 LSB Gain Error ± 0.5 ± 4.0 LSB Gain Temperature Coefficient ± 0.25 ppm/°C Dynamic Specifications (10kHz sine-wave input, 0V to 2.500Vpp, 200ksps, 3.2MHz external clock) Signal-to-Noise + Distortion Ratio SINAD 70 73 dB Total Harmonic Distortion THD Up to the 5 th harmonic -88 -80 dB Spurious-Free Dynamic Range SFDR 76 80 dB Small-Signal Bandwidth -3dB roll off 3.8 MHz Conversion Rate Sampling Time (= Track/Hold Acquisition Time) tACQ Ext. Clock = 3.2MHz, 2.5 clocks/ acquisi- tion 0.781 µs Ext. Clock = 3.2MHz, 12 clocks/ conver- sion 3.75 µs Conversion Time tCONV Int. Clock = 3.2MHz +/- 12% tolerance 3.30 4.20 µs Aperture Delay 30 ns Aperture Jitter < 50 ps External Clock Frequency 0.1 3.2 MHz Internal Clock Frequency 2.81 3.2 3.58 MHz Analog Inputs Unipolar, COM = 0V 0 to VREF Input Voltage Range, Single- Ended and Differential Bipolar, COM = VREF/2 ± VREF / 2 V Input Capacitance 16 pF |
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