©2008 CADEKA Microcircuits LLC

www.cadeka.com

12

ADVANCE Data Sheet

a recommended configuration using a transformer. Make

sure that a transformer with sufficient linearity is selected,

and that the bandwidth of the transformer is appropriate.

The bandwidth should exceed the sampling rate of the

ADC with at least a factor of 10. It is also important to

keep phase mismatch between the differential ADC inputs

small for good HD2 performance. This type of transformer

coupled input is the preferred configuration for high fre-

quency signals as most differential amplifiers do not have

adequate performance at high frequencies. If the input

signal is traveling a long physical distance from the signal

source to the transformer (for example a long cable), kick-

backs from the ADC will also travel along this distance. If

these kick-backs are not terminated properly at the source

side, they are reflected and will add to the input signal at

the ADC input. This could reduce the ADC performance.

To avoid this effect, the source must effectively terminate

the ADC kick-backs, or the traveling distance should be

very short. If this problem could not be avoided, the cir-

cuit in Figure 6 can be used.

Figure 4. Transformer-Coupled Input

Figure 5 shows AC-coupling using capacitors. Resistors

differential input signals to the correct voltage. The series

capacitor, CI, form the high-pass pole with these resistors,

and the values must therefore be determined based on

the requirement to the high-pass cut-off frequency.

Figure 5. AC-Coupled Input

Note that startup time from Sleep Mode and Power Down

Mode will be affected by this filter as the time required

to charge the series capacitors is dependent on the filter

cut-off frequency.

If the input signal has a long traveling distance, and the

kick-backs from the ADC not are effectively terminated at

the signal source, the input network of Figure 6 can be used.

The configuration is designed to attenuate the kickback

from the ADC and to provide an input impedance that looks

as resistive as possible for frequencies below Nyquist.

Values of the series inductor will however depend on board

design and conversion rate. In some instances a shunt ca-

pacitor in parallel with the termination resistor (e.g. 33pF)

may improve ADC performance further. This capacitor at-

tenuate the ADC kick-back even more, and minimize the

kicks traveling towards the source. However, the imped-

ance match seen into the transformer becomes worse.

Figure 6. Alternative Input Network

Clock Input And Jitter Considerations

Typically high-speed ADCs use both clock edges to gener-

ate internal timing signals. In the CDK1307 only the rising

edge of the clock is used. Hence, input clock duty cycles

between 20% and 80% is acceptable.

The input clock can be supplied in a variety of formats.

The clock pins are AC-coupled internally, and hence a wide

common mode voltage range is accepted. Differential

clock sources as LVDS, LVPECL or differential sine wave

can be connected directly to the input pins. For CMOS

inputs, the CLKN pin should be connected to ground, and

the CMOS clock signal should be connected to CLKP. For

differential sine wave clock input the amplitude must be

33

33

47

pF

pF

120nH

120nH

33

33

68

220

optional

1:1