| 전자부품 데이터시트 검색엔진 |
|
AI4100 데이터시트(PDF) 9 Page - A1 PROs co., Ltd. |
|
|
|||||||||||||||||||||||||||||
AI4100 데이터시트(HTML) 9 Page - A1 PROs co., Ltd. |
|
9 / 18 page ![]() Address R/W A3 A2 A1 A0 00 1 0 1 0 0 1 1 0 0 0 0 0 1 Register Name Function Description W 0 Mode 1 DOUT timing control/OUTCK polarity/ADCLK polarity/ADIN connection/ADC output/Black level reset/Power down W 0 Mode 2 Clamp current/ADIN clamp/Clamp target/S/H, enable logic/Monitor selection W 0 Mode 3 / CDS gain CDS gain control/Black loop gain boost/Boost period W 0 PGA gain PGA gain W 0 Black level ADC code at black level (1 LSB step) O O O O √ O D0 O O O ----- O √ O D1 O O --------------- O O √ O D2 O O √ O ----- O √ O D3 O O O O O D4 O O ----- O ----- O ----- O D5 -------------------------------------------------- 1 O X √ O √ O D6 X O X √ O √ O D7 X Functions X Default ---------------------------------------------------------------- O Functions PGA gain X Functions CDS gain control Black loop gain boost Boost period PGA Gain X √ O D8 Black level Black Level X Default X Default Mode 3 Monitor selection S/H, enable logic Clamp target ADIN clamp Clamp current Functions X Default Mode 2 Power down Black level reset ADC output Reserved ADIN connection ADCLK polarity OUTCK polarity DOUT timing control Functions X Default Mode 1 D9 Register Map Register Bit Assignment 9 A i4100 |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |