SN74ALVC7803

512

× 18

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SDAS274 – JANUARY 1995

13

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

VOH

VOL

th

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

S1

6 V

Open

GND

500

Ω

500

Ω

tPLH

tPHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note C)

Output

Waveform 2

S1 at GND

(see Note C)

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

1.5 V

1.5 V

3 V

0 V

1.5 V

1.5 V

VOH

VOL

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

0 V

1.5 V

3 V

0 V

1.5 V

1.5 V

0 V

3 V

0 V

1.5 V

1.5 V

tw

Input

(see Note B)

3 V

3 V

3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Output

Input

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR

v10 MHz, ZO = 50 Ω, trv2.5 ns, tfv2.5 ns.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

3-STATE OUTPUTS (ANY Q)

PARAMETER

R1, R2

CL†

S1

t

tPZH

500

Ω

50 pF

GND

ten

tPZL

500

Ω

50 pF

6 V

tdi

tPHZ

500

Ω

50 pF

GND

tdis

tPLZ

500

Ω

50 pF

6 V

tpd

tPLH /tPHL

500

Ω

50 pF

Open

† Includes probe and test-fixture capacitance

Figure 8. Standard CMOS Outputs (FULL, EMPTY, HF, AF/AE)