SN74AS298A

QUADRUPLE 2-INPUT MULTIPLEXER

WITH STORAGE

SDAS219B – DECEMBER 1983 – REVISED DECEMBER 1994

4

POST OFFICE BOX 655303

switching characteristics over recommended ranges of supply voltage and operating free-air

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

MIN

MAX

UNIT

fmax

62

MHz

tPLH

CLK

Q

2

9

ns

tPHL

CLK

Q

1

11

ns

APPLICATION INFORMATION

This versatile multiplexer can be connected to operate as a shift register that can shift n places in a single clock pulse.

Figure 1 illustrates a BCD shift register that shifts an entire 4-bit BCD digit in one clock pulse.

1, 2D

1, 2D

1, 2D

1, 2D

1, 2D

1, 2D

SN74AS298A

Digit 1

Digit 2

Digit 3

Parallel Load

WS

CLK

A1

A2

B1

B2

C1

C2

D1

D2

A1

A2

B1

B2

C1

C2

D1

D2

A1

A2

B1

B2

C1

C2

D1

D2

G1

C2

G1

C2

G1

C2

MUX

MUX

MUX

QA

QB

QC

QD

QA

QB

QC

QD

QA

QB

QC

QD

SN74AS298A

SN74AS298A

Figure 1. BCD Shift Register

When WS is high and the registers are clocked, the content of register 1 is transferred (shifted) to register 2, etc.,

effectively shifting the BCD digits one position. This application also retains a parallel-load capability, which means

that new BCD data can be entered into the entire register with one clock pulse. This arrangement can be modified

to perform the shifting of binary data for any number of bit locations.

Another function that can be implemented is a register designed specifically for supporting multiplier or division

operations (see Figure 2).

When WS is low and the register is clocked, the outputs of the arithmetic / logic units (ALUs) are shifted one place.

When WS is high and the registers are clocked, the data is shifted two places.