SN74LVC1G00

SINGLE 2INPUT POSITIVENAND GATE

SCES212T − APRIL 1999 − REVISED JUNE 2005

2

POST OFFICE BOX 655303

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE PART NUMBER

TOP-SIDE MARKING‡

NanoStar

 − WCSP (DSBGA)

0.17-mm Small Bump − YEA

SN74LVC1G00YEAR

NanoFree

 − WCSP (DSBGA)

0.17-mm Small Bump − YZA (Pb-free)

Reel of 3000

SN74LVC1G00YZAR

_ _ _CA_

NanoStar

 − WCSP (DSBGA)

0.23-mm Large Bump − YEP

Reel of 3000

SN74LVC1G00YEPR

_ _ _CA_

−40

°C to 85°C

NanoFree

 − WCSP (DSBGA)

0.23-mm Large Bump − YZP (Pb-free)

SN74LVC1G00YZPR

SOT (SOT-23) − DBV

Reel of 3000

SN74LVC1G00DBVR

C00_

SOT (SOT-23) − DBV

Reel of 250

SN74LVC1G00DBVT

C00_

SOT (SC-70) − DCK

Reel of 3000

SN74LVC1G00DCKR

SOT (SC-70) − DCK

Reel of 250

SN74LVC1G00DCKT

CA_

SOT (SOT-553) − DRL

Reel of 4000

SN74LVC1G00DRLR

CA_

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.

YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,

FUNCTION TABLE

INPUTS

OUTPUT

A

B

OUTPUT

Y

H

H

L

L

XH

X

L

H

logic diagram (positive logic)

1

2

4

A

B

Y