SN75124

TRIPLE LINE RECEIVER

SLLS058B – SEPTEMBER 1973 – REVISED MAY 1995

2

POST OFFICE BOX 655303

2Y

15

12

11

10

6

5

4

3

2

1

14

3Y

1Y

9

7

13

3A

3S

3R

2B

2A

2S

2R

1B

1A

1S

1R

≥ 1

&

&

&

† This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

≥ 1

logic diagram (positive logic)

3A

3S

3R

2B

2A

2S

2R

1B

1A

1S

1R

9

7

13

1Y

2Y

3Y

12

11

10

6

5

4

3

2

1

15

14

schematic (each receiver)

58

Ω

13, 7, 9

Y

800

Ω

4 k

Ω

4 k

Ω

A

B‡

1, 5, 12

2, 6

S

15, 4, 11

16

VCC

14, 3, 10

R

8

GND

...VCC bus

To Other

Receivers

V

V

V

V

To Other

Receivers

‡ B input is provided on receivers 1 and 2 only

Resistor values shown are nominal.