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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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S12CPUV2 데이터시트(PDF) 61 Page - Motorola, Inc |
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S12CPUV2 데이터시트(HTML) 61 Page - Motorola, Inc |
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61 / 138 page  MC9S12DT128 Device User Guide — V02.09 61 RESET ———— VDDR None None External Reset TEST ———— N.A. None None Test Input VREGEN ———— VDDX NA NA Voltage Regulator Enable Input XFC ———— VDDPLL NA NA PLL Loop Filter BKGD TAGHI MODC — — VDDR Always Up Up Background Debug, Tag High, Mode Input PAD[15] AN1[7] ETRIG1 — — VDDA None None Port AD Input, Analog Inputs, External Trigger Input (ATD1) PAD[14:8] AN1[6:0] — — — VDDA None None Port AD Input, Analog Inputs (ATD1) PAD[7] AN0[7] ETRIG0 — — VDDA None None Port AD Input, Analog Inputs, External Trigger Input (ATD0) PAD[6:0] AN0[6:0] — — — VDDA None None Port AD Input, Analog Inputs (ATD0) PA[7:0] ADDR[15:8]/ DATA[15:8] — — — VDDR PUCR/ PUPAE Disabled Port A I/O, Multiplexed Address/Data PB[7:0] ADDR[7:0]/ DATA[7:0] — — — VDDR PUCR/ PUPBE Disabled Port B I/O, Multiplexed Address/Data PE7 NOACC XCLKS — — VDDR PUCR/ PUPEE Mode depen- dant1 Port E I/O, Access, Clock Select PE6 IPIPE1 MODB — — VDDR While RESET pin low: Down Port E I/O, Pipe Status, Mode Input PE5 IPIPE0 MODA — — VDDR Port E I/O, Pipe Status, Mode Input PE4 ECLK — — — VDDR PUCR/ PUPEE Mode depen- dant1 Port E I/O, Bus Clock Output PE3 LSTRB TAGLO — — VDDR Port E I/O, Byte Strobe, Tag Low PE2 R/W — — — VDDR Port E I/O, R/W in expanded modes PE1 IRQ — — — VDDR Up Port E Input, Maskable Interrupt PE0 XIRQ — — — VDDR Port E Input, Non Maskable Interrupt PH7 KWH7 --- — — VDDR PERH/ PPSH Disabled Port H I/O, Interrupt PH6 KWH6 --- — — VDDR PERH/ PPSH Disabled Port H I/O, Interrupt PH5 KWH5 --- — — VDDR PERH/ PPSH Disabled Port H I/O, Interrupt Pin Name Function 1 Pin Name Function 2 Pin Name Function 3 Pin Name Function 4 Pin Name Function 5 Powered by Internal Pull Resistor Description CTRL Reset State |
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