CS

SE

Only

5-Bit Shift Register

ODD\

SELECT0

EN

MUX

Analog

START

SGL\

SELECT1

Circuits

To Internal

(see Note A)

DI

CLK

CS

R

D

CLK

TLC0838

TLC0838

TLC0834

CH7

CH5

CH6

COM

CH4

CH3

CH2

CH1

CH0

Comparator

SARS

CS

R

Start

S

CLK

CLK

Delay

Time

S

R

CS

DO

CS

CS

D

CLK

R

EOC

Register

Shift

9-Bit

R

CLK

First

LSB

Bit 1

Bits 0–7

First

MSB

Shot

One

Latch

and

Logic

SAR

R

CS

Bits 0–7

REF

Decoder

and

Ladder

EN

Flip-Flop

functional block diagram

NOTE A: For the TLC0834, DI is input directly to the D input of SELECT1; SELECT0 is forced to a high.

EVEN

DIF

18

15

14

18

18

18

18

12

16

18

17

1

2

3

4

5

6

7

8

9

18

B: Terminal numbers shown are for the DW or N package.