TLC320AC02C datasheet(13/84 Pages) TI

13 / 84 page

1–6

1.4

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.†

NO.‡

I/O

DESCRIPTION

OUT+

Noninverting output of analog output power amplifier. OUT+ can drive transformer

hybrids or high-impedance loads directly in a differential connection or a

single-ended configuration with a buffered VMID.

OUT–

Inverting output of analog output power amplifier. OUT– is functionally identical

with and complementary to OUT+.

PWR DWN

Power-down input. When PWR DWN is taken low, the device is powered down

such that the existing internally programmed state is maintained. When PWR

DWN is brought high, full operation resumes.

RESET

Reset input that initializes the internal counters and control registers. RESET

initiates the serial data communications, initializes all of the registers to their

default values, and puts the device in a preprogrammed state. After a low-going

pulse on RESET, the device registers are initialized to provide a 16-kHz

data-conversion rate and 7.2-kHz filter bandwidth for a 10.368-MHz master clock

input signal.

SCLK

I/O

Shift clock. SCLK clocks the digital data into DIN and out of DOUT during the

frame-synchronization interval. When configured as an output (M/S high), SCLK

is generated internally by dividing the master clock signal frequency by four. When

configured as an input (M/S low), SCLK is generated externally and

synchronously to the master clock. This signal clocks the serial data into and out

of the device.

SUBS

Substrate connection. SUBS should be tied to ADC GND.

† Terminal numbers shown are for the FN package.

‡ Terminal numbers shown are for the PM package.

TLC320AC02C 데이터시트(PDF) 13 Page - Texas Instruments