TLC320AC01 datasheet(15/90 Pages) TI

15 / 90 page

2–1

Detailed Description

2.1

Definitions and Terminology

ADC Channel

All signal processing circuits between the analog input and the digital conversion

results at DOUT

Codec Mode

The operating mode under which the device receives shift clock and frame-sync

signals from a host processor. The device has no slaves.

The d represents valid programmed or default data in the control register format

(see Section 2.19) when discussing other data-bit portions of the register.

Dxx

Bit position in the primary data word (xx is the bit number)

DAC Channel

All signal processing circuits between the digital data word applied to DIN and the

differential output analog signal available at OUT+ and OUT–

Data Transfer Interval The time during which data is transferred from DOUT and to DIN. This interval is 16

shift clocks regardless of whether the shift clock is internally or externally generated.

The data transfer is initiated by the falling edge of the frame-sync signal.

DSxx

Bit position in the secondary data word (xx is the bit number)

FCLK

An internal clock frequency that is a division of MCLK that controls the low-pass filter

and (sinx)/x filter clock (see Figure 1–1 and Table 1-1).

The analog input frequency of interest

Frame Sync

The falling edge of the signal that initiates the data-transfer interval. The primary

frame sync starts the primary communications, and the secondary frame sync starts

the secondary communications.

Frame Sync and

The time between falling edges of successive primary frame-sync signals

Sampling Period

Frame-Sync Interval

The time period occupied by 16 shift clocks. Regardless of the mode of operation,

there is always an internal frame-sync interval signal that goes low on the rising

edge of SCLK and remains low for 16 shift clocks. It is used for synchronization of

the serial-port internal signals. It goes high on the seventeenth rising edge of SCLK.

The sampling frequency that is the reciprocal of the sampling period.

Host

Any processing system that interfaces to DIN, DOUT, SCLK, or FS.

Master Mode

The operating mode under which the device generates and uses its own shift clock

and frame-sync signal and generates all delayed frame-sync signals necessary to

support slave devices.

Phase Adjustment

The programmed time variation from the falling edge of one frame-sync signal to the

falling edge of the next frame sync signal. The time variation is determined by the

contents of the A

′ register. Since the time between falling edges of successive

frame-sync signals is the the sampling period, the sampling period is adjusted.

Primary (Serial)

The digital data-transfer interval. Since the device is synchronous, the signal data

Communications

words from the ADC channel and to the DAC channel occur simultaneously.

Secondary (Serial)

The digital control and configuration data-transfer interval into DIN and the register

Communications

read-data cycle from DOUT. The data-transfer interval occurs when requested by

hardware or software.

Signal Data

The input signal and all of the converted representations through the ADC channel

and return through the DAC channel to the analog output. This is contrasted with

the purely digital software-control data.

Slave Mode

The operating mode under which the device receives shift clock and frame-sync

signals from a master device.

TLC320AC01 데이터시트(PDF) 15 Page - Texas Instruments

TLC320AC01 데이터시트(HTML) 15 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

데이터시트 다운로드

링크 URL