4

21737-0931, Rev. A

04-05-2006

18

19

3

TX DATA IN+

Vcc

3.3V

15

1 H coil or ferrite bead

µ

(<0.2

series resistance)

Ω

0.1

TX DATA IN-

TX Disable

16

0.1

+

10

50

line

Ω

1, 9,10,11,14,17,20

0.1

+

10

(100

to ground internally)

Ω

to 50

load

Ω

Vcc

3.3V

RX DATA OUT+

13

12

RX DATA OUT-

5

4

6

MOD_DEF(0)

MOD_DEF(1)

MOD_DEF(2)

LOS

8

R

R

R

50

line

Ω

50

line

Ω

50

line

Ω

to 50

load

Ω

100

TRXNFEMM

Example of SFP host board schematic

TRXNFEMM

R: 4.7 to 10k

Ω

Ω

Ω

Ω

Ω

Application Notes

Electrical interface: All signal interfaces are compliant

with the SFP MSA specification. The high speed DATA

interface is differential AC-coupled internally and can be

directly connected to a 3.3V SERDES IC. All low speed

control and sense output signals are open collector TTL

compatible and should be pulled up with a 4.7 - 10k

Ω

resistor on the host board.

Loss of Signal (LOS): The Loss of Signal circuit monitors

the level of the incoming optical signal and generates a logic

HIGH when an insufficient photocurrent is produced.

TX Fault: Per SFP MSA, pin 2 is TX Fault. This transceiver

is LED based and does not support TX Fault. Pin 2 is

internally connected to transmitter circuit ground (TX GND)

to indicate normal operation.

TX Disable: When the TX Disable pin is at logic HIGH, the

transmitter optical output is disabled (less than -45dBm).

Serial Identification: The module definition of SFP

is indicated by the three module definition pins,

MOD_DEF(0), MOD_DEF(1) and MOD_DEF(2). Upon

power up, MOD_DEF(1:2) appear as NC (no connection),

Figure 1 - Trade-off curves in FDDI PMD document

100

120

140

160

180

200

1280

1300

1320

1340

1360

1380

SOURCE CENTER WAVELENGTH (nm)

1.5

2.0

2.5

3.0

3.5

3.0

3.5

Source rise & fall time (ns)