TMS320UC5402 datasheet(46/63 Pages) TI

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TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

reset, BIO, interrupt, and MP/MC timings

timing requirements for reset, BIO, interrupt, and MP/MC [H = 0.5 tc(CO)] (see Figure 21, Figure 22,

and Figure 23)

MIN

MAX

UNIT

MIN

MAX

UNIT

th(RS)

Hold time, RS after CLKOUT low

th(BIO)

Hold time, BIO after CLKOUT low

–2

th(INT)

Hold time, INTn, NMI, after CLKOUT low†

–3

th(MPMC)

Hold time, MP/MC after CLKOUT low

tw(RSL)

Pulse duration, RS low‡§

4H+5

tw(BIO)S

Pulse duration, BIO low, synchronous

2H+4

tw(BIO)A

Pulse duration, BIO low, asynchronous

tw(INTH)S

Pulse duration, INTn, NMI high (synchronous)

2H–1

tw(INTH)A

Pulse duration, INTn, NMI high (asynchronous)

tw(INTL)S

Pulse duration, INTn, NMI low (synchronous)

2H+1

tw(INTL)A

Pulse duration, INTn, NMI low (asynchronous)

tw(INTL)WKP

Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup

tsu(RS)

Setup time, RS before X2/CLKIN low¶

tsu(BIO)

Setup time, BIO before CLKOUT low

tsu(INT)

Setup time, INTn, NMI, RS before CLKOUT low

tsu(MPMC)

Setup time, MP/MC before CLKOUT low

† The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs

with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is

corresponding to three CLKOUT sampling sequences.

‡ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50

µs to ensure

synchronization and lock-in of the PLL.

§ Note that RS may cause a change in clock frequency, therefore changing the value of H.

¶ Divide-by-two mode

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