TMS320VC549 datasheet(93/111 Pages) TI

93 / 111 page

TMS320C54x, TMS320LC54x, TMS320VC54x

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

buffered serial port receive timing

timing requirements for buffered serial port receive (see Figure 35)

’C54x-40

’LC54x-40

’54x-50

’54x-66

UNIT

MIN

MAX

MIN

MAX

UNIT

tc(SCK)

Cycle time, serial port clock

†

tf(SCK)

Fall time, serial port clock

tr(SCK)

Rise time, serial port clock

tw(SCK)

Pulse duration, serial port clock low/high

8.5

tsu(BFSR)

Setup time, BFSR before BCLKR falling edge (see Note 2)

th(BFSR)

Hold time, BFSR after BCLKR falling edge (see Note 2)

tc(SCK)–2‡

tsu(BDR)

Setup time, BDR before BCLKR falling edge

th(BDR)

Hold time, BDR after BCLKR falling edge

† The serial port design is fully static and therefore can operate with tc(SCK) approaching infinity. It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

‡ First bit is read when BFSR is sampled low by BCLKR clock.

NOTE 2: Timings for BCLKR and BFSR are given with polarity bits (BCLKP and BFSP) set to 0.

tw(SCK)

BCLKR

BFSR

BDR

8/10/12/16

tsu(BDR)

tc(SCK)

tsu(BFSR)

th(BFSR)

th(BDR)

tr(SCK)

tf(SCK)

Figure 35. Buffered Serial Port Receive Timing

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