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TMS320VC549 데이터시트(PDF) 101 Page - Texas Instruments

부품명 TMS320VC549
상세설명  FIXED-POINT DIGITAL SIGNAL PROCESSORS
PDF  111 Pages
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TMS320VC549 데이터시트(HTML) 101 Page - Texas Instruments

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TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
101
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
host-port interface timing
switching characteristics over recommended operating conditions for host-port interface
[H = 0.5tc(CO)] (see Note 5, Note 6, and Figure 40 through Figure 43)
PARAMETER
’C54x-40
’C54x-50
’C54x-66
UNIT
MIN
MAX
td(DSL-HDV)
Delay time, DS low to HD driven
5
12
ns
Case 1: Shared-access mode if
tw(DSH) < 7H
7H+20–tw(DSH)
t
Delay time, HDS falling to HD valid for first byte
Case 2: Shared-access mode if
tw(DSH) > 7H
20
ns
td(HEL-HDV1)
Delay time, HDS falling to HD valid for first byte
of a non-subsequent read:
→ max 20 ns†‡
Case 3: Host-only mode if
tw(DSH) < 20 ns
40–tw(DSH)
ns
Case 4: Host-only mode if
tw(DSH) > 20 ns
20
td(DSL-HDV2)
Delay time, DS low to HD valid, second byte
5‡
20
ns
td(DSH-HYH)
Delay time, DS high to HRDY high
10H+10
ns
tsu(HDV-HYH)
Setup time, HD valid before HRDY rising edge
3H–10
ns
th(DSH-HDV)R
Hold time, HD valid after DS rising edge, read
0
12
ns
td(COH-HYH)
Delay time, CLKOUT rising edge to HRDY high
10
ns
td(DSH-HYL)
Delay time, HDS or HCS high to HRDY low
12
ns
td(COH-HTX)
Delay time, CLKOUT rising edge to HINT change
15
ns
† Host-only mode timings apply for read accesses to HPIC or HPIA, write accesses to BOB, and resetting DSPINT or HINT to 0 in shared-access
mode. HRDY does not go low for these accesses.
‡ Shared-access mode timings will be met automatically if HRDY is used.
NOTES:
5. SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRL0, HCNTRL1, and HR / W.
HDS refers to either HDS1 or HDS2.
DS refers to the logical OR of HCS and HDS.
6. On host read accesses to the HPI, the setup time of HD before DS rising edge depends on the host waveforms and cannot be
specified here.



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