TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C – FEBRUARY 1990 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443

interrupts (continued)

chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending

interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and

priority conditions.

The TMS370Cx32 has 22 hardware system interrupts (plus RESET) as shown in Table 7. Each system interrupt

has a dedicated vector located in program memory through which control is passed to the interrupt service

routines. A system interrupt may have multiple interrupt sources. All the interrupt sources are individually

maskable by local interrupt enable control bits in the associated peripheral file. Each interrupt source FLAG bit

is individually readable for software polling or for determining which interrupt source generated the associated

system interrupt.

Nineteen of the system interrupts are generated by on-chip peripheral functions, and three external interrupts

are supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3

control registers in peripheral file frame 1. Each external interrupt is individually software configurable for input

polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as

either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked

by the individual- or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and,

therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility,

external interrupts INT2 and INT3 can be software configured as general-purpose input/output pins if the

interrupt function is not required (INT1 can be similarly configured as an input pin).