TMS370 datasheet(7/73 Pages) TI

7 / 73 page

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

modes

The TMS370Cx6x has four operating modes, two basic modes with each mode having two memory

configurations. The basic operating modes are the microcomputer and microprocessor modes, which are

selected by the voltage level applied to the dedicated MC pin two cycles before RESET goes inactive. The two

memory configurations then are selected through software programming of the internal system configuration

registers. The four operating modes are the microcomputer single chip, microcomputer with external expansion,

microprocessor without internal program memory, and microprocessor with internal program memory. These

modes are described in the following list.

D Microcomputer single chip mode:

–

Operates as a self-contained microcomputer with all memory and peripherals on-chip

–

Maximizes the general-purpose I/O capability for real-time control applications

D Microcomputer with external expansion mode:

–

Supports bus expansion to external memory or peripherals, while all on-chip memory (RAM, ROM,

EPROM, and data EEPROM) remains active

–

Configures digital I/O ports (ports A, B, C, and D) through software, under control of the associated port

control, to become external memory as follows:

–

Port A: 8-bit data memory

–

Port B and Port C: 16-bit address memory

–

Port D: 5-bit control memory (pin not used as function A or B can be configured as I/O)

–

Utilizes the pins available (not used for address, data, or control memory) as general-purpose

input/output by programming them individually

–

Lowers the system cost by not requiring an external address/data latch (address memory and data

memory are nonmultiplexed)

–

Reduces external interface decode logic by using the precoded chip select outputs that provide direct

memory/peripheral chip select or chip enable functions

–

Function A maps up to 24K bytes of external memory into the address space by using CSE1 and CSH1

as memory-bank selects under software control.

–

Function B maps up to 24K bytes of external memory into the address space by using EDS under

software control.

D Microprocessor without internal program memory mode:

–

Ports A, B, C, and D (these ports are not programmable) become the address, data, and control buses

for interface to external memory and peripherals.

–

On-chip RAM and data EEPROM remain active, while the on-chip ROM or EPROM is disabled.

–

Program area and the reset, interrupt, and trap vectors are located in off-chip memory locations.

D Microprocessor with internal program memory mode:

–

Configured as the microprocessor without internal program memory mode with respect to the external

bus interface

–

Application program in external memory enables the internal program ROM or EPROM to be active in

the system. (Writing a zero to the MEMORY DISABLED control bit (SCCR1.2) of the SCCR1 control

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