TNETE2201A

1.25-GIGABIT ETHERNET TRANSCEIVER

SLLS342 – MARCH 1999

12

POST OFFICE BOX 655303

transmitter timing requirements over recommended operating conditions (unless otherwise

noted)

TEST CONDITIONS

MIN

NOM

MAX

UNIT

tsu1

Setup time, TD0 – TD9 valid to REFCLK

↑

See Figure 4

2

ns

th1

Hold time, REFCLK

↑ to TD0 – TD9 invalid

See Figure 4

1

ns

Parallel-to-serial data latency

9

ns

transmit interface timing

The transmit interface is defined in the 10 b spec as the 10-bit parallel data input to the physical layer for serial

transmission. The timing values are specified from REFCLK midpoint to valid input signal levels or from valid

input signal levels to REFCLK midpoint.

TD0 – TD9

Valid

Valid

Valid

50%

tsu1

th1

REFCLK

Figure 4. Transmit 10-Bit Interface Timing Waveforms