TMS77C82 datasheet(34/77 Pages) TI

34 / 77 page

TMS370Cx5x

8-BIT MICROCONTROLLER

SPNS010F – DECEMBER 1986 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

timer 2A module (continued)

The T2A dual-compare mode block diagram is illustrated in Figure 12. The annotations on the diagram identify

the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh,

bit 0, in the T2ACTL2 register.

T2AC.15-0

T2ACTL2.1

T2ACTL3.2

T2ACTL3.1

T2ACTL3.5

T2ACTL3.3

Clock

Source

16-Bit

Counter

16-Bit

Compare=

Reset

T2AC1

RST ENA

T2A SW

RESET

Edge 1

Select

T2AEDGE1 DET ENA

Output

Enable

Capt/Comp

MSB

LSB

MSB

LSB

T2AEDGE1

OUT ENA

T2AIC1/CR

T2AEDGE1 POLARITY

16-Bit

Compare

MSB

LSB

T2ACC.15-0

T2AC1 INT FLAG

T2ACTL2.0

T2ACTL2.5

T2AC1 INT ENA

T2AC2 INT FLAG

T2ACTL2.6

T2AC2 INT ENA

T2A OVRFL INT FLAG

T2ACTL1.4

T2ACTL1.3

T2A OVRFL INT ENA

T2AEDGE1 INT FLAG

T2ACTL2.2

T2ACTL2.7

T2AEDGE1 INT ENA

T2A PRIORITY

T2AC2 OUT ENA

T2AC1 OUT ENA

T2ACTL3.6

T2AIC2/PWM

T2APC2.7-4

T2APRI.6

T2ACNTR.15-0

T2ACTL1.0

T2ACTL3.4

T2AEDGE1

RST ENA

T2APC2.3-0

T2ACTL3.0

Level 1 Int

Level 2 Int

Figure 12. Dual-Compare Mode

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