ASM1232LPSF datasheet(2/10 Pages) PULSECORE

2 / 10 page

Notice: The information in this document is subject to change without notice

rev 1.6

November 2006

ASM1232LP/LPS

2 of 10

5V µP Power Supply Monitor and Reset Circuit

Pin Configuration

Pin Description

Pin #

8-Pin Package

Pin #

16-Pin Package

Name

Function

PBRST

Debounced manual pushbutton RESET input.

Watchdog time delay selection. (tTD = 150ms for TD = GND, tTD = 610ms

for TD=Open, and tTD = 1200ms for TD = VCC).

TOL

Selects 5% (TOL connected to GND) or 10% (TOL connected to VCC)

trip point tolerance.

GND

Ground.

RESET

Active HIGH reset output. RESET is active:

1. If VCC falls below the reset voltage trip point.

2. If PBRST is LOW.

3. If ST is not strobed LOW before the timeout period set by TD expires.

4. During power-up.

RESET

Active LOW reset output. (See RESET).

713

Strobe input.

815

VCC

5V power.

1,3,5,7,

10,12,14,16

No internal connection.

PBRST

TOL

GND

VCC

RESET

PBRST

TOL

GND

VCC

RESET

ASM1232LPS

ASM1232LPU

DIP/SO/MicroSO

ASM1232LP

ASM1232LPS-2

ASM1232LPSF 데이터시트(PDF) 2 Page - PulseCore Semiconductor

ASM1232LPSF 데이터시트(HTML) 2 Page - PulseCore Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10

데이터시트 다운로드

링크 URL